Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to semiconductor devices and manufacturing methods for the same.
Related Art
At present, in the advanced complementary metal oxide semiconductor (CMOS) technology, a static random access memory (SRAM) operated using Sub-1V (that is, a working voltage less than 1 V) faces problems caused by a decrease in the read/write stability. One of the root causes is contradictory requirements on read/write operations. FIG. 1A is a schematic circuit connection diagram of a 6-transistor-SRAM (6T-SRAM) in the prior art. FIG. 1A shows a first Pass Gate (PG) transistor 11, a second PG transistor 12, a first pull up (PU) transistor 13, a second PU transistor 14, a first pull down (PD) transistor 15, and a second PD transistor 16. In addition, FIG. 1A further shows internal nodes A and B, a bit line BL, a complementary bit line BLb, a word line WL, a supply voltage Vdd, and the like.
FIG. 1B shows a read current Iread in a read operation process. For example, the read current Iread flows from the bit line BL to a ground terminal through the first PG transistor 11 and the first PD transistor 15, so as to read data stored in the node A. FIG. 1C shows a write current Iwrite in a write operation process. For example, the write current Iwrite flows from the supply voltage Vdd to the complementary bit line BLb through the second PU transistor 14 and the second PG transistor 12, so that “1” originally stored in the node B can be written as “0”, and “0” originally stored in the node A can be written as “1”. Currently, when read and write operations are performed, it is necessary to improve the read margin and write margin of the SRAM, thereby improving the anti-interference capability thereof.